Technical Inquiry regarding DPCU Block for CPRI IP Single-Trip Delay Calibration

I am currently implementing the "single-trip delay calibration" feature using the Intel CPRI IP core.

According to the User Guide (ID: 683595, Version: 2021.11.11), this feature requires the Dynamic Phase Control Unit (DPCU) block. The documentation states that "Intel provides the DPCU block with the CPRI IP." However, I am having difficulty locating this specific module.

Could you please clarify where this DPCU block is located or how it should be instantiated?

My design environment is as follows:

• Quartus Prime Version: 20.4 Pro
• Device Part Number: Arria 10 (10AS032H2F34I2SG)
• CPRI IP Version: 19.4.0
• Reference Document: CPRI Intel FPGA IP User Guide (ID: 683595)

Best regards!