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Adithiya_R's avatar
Adithiya_R
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5 months ago

Intel P-tile HIP clock not visible during timing analysis "all clock report"

Hi Everyone, We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logi...
Pcie
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
5 months ago

Hi,

I'm helping the PCIe part.


PLD_CLOCK_FREQ will eventually reflect as coreclkout_hip, is it ?

--Yes


And sof is working perfect for Gen3 and not working for gen4 where PLD_CLK_FREQ is the only change. why is that ?

--Probably the user logic part is not able to run correctly at 350MHz.


Regards,

Rong