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Adithiya_R
New Contributor
New ContributorIntel P-tile HIP clock not visible during timing analysis "all clock report"
Hi Everyone, We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logi...
Adithiya_RNew Contributor
New ContributorHi Sheng
- We generate the intel Ptile ip with our custom logic instead of PIO, and these are the following ports, which are given below
rx/tx_pma_parllel_clk, ref_clk these are the only list getting visible, coreclkout_hip which is supposed to be 350 Mhz (gen4) or 250 Mhz(gen3) is not in the list
- Requirement : To perform timing analysis with respect to coreclkouthip or the corresponding port in custom logic (user_clk)
