Forum Discussion
New ContributorAVST FIFO and AVST Demultiplexer IP Simulation Behavior
Hi,
I am using Quartus version 25.3. I simulated 2 IP's independently and had questions about their behavior.
1. For the Avalon Streaming (AVST) Demultiplexer IP (figure 1) , is there a reason why the endofpacket (eop) signal remains asserted after the packet leaves the output, when I simulate with packet support (figure 2)? Is this normal? AVST Demultiplexer IP version 19.3.1.
2. For the AVST SC FIFO (Figure 3) , is there a reason the negative edge of output eop is unknown (red) (Figure 4)? Is this normal? AVST SC FIFO version 19.3.2.
Thank you for the help!
AVST Demultiplexer Parameters:
AVST Demultiplexer Waveform:
AVST SC FIFO Parameters:
AVST SC FIFO Waveform:
Sorry for the delay.
1) Yes, this behavior is normal. The endofpacket signal is only meaningful when valid is asserted. When valid is deasserted, all output signals are considered don’t-care and may retain their previous values. In this case, the demultiplexer IP is simply holding the last value of endofpacket.
2) Yes, this behavior is also normal in simulation for the Avalon Streaming Single Clock FIFO and does not indicate a functional issue, provided the packet completes correctly during the last cycle when out_valid is asserted. In AVST, the out_valid qualifies every other source output. The sink should only sample data, sop, eop, empty, etc., on cycles where valid (and ready, for a transfer) are asserted. When out_valid is low, out_eop is considered a don’t-care and may appear as X(red) in simulation.
Regards,
Richard Tan
5 Replies
- RichardT_altera
Super Contributor
Sorry for the delay.
1) Yes, this behavior is normal. The endofpacket signal is only meaningful when valid is asserted. When valid is deasserted, all output signals are considered don’t-care and may retain their previous values. In this case, the demultiplexer IP is simply holding the last value of endofpacket.
2) Yes, this behavior is also normal in simulation for the Avalon Streaming Single Clock FIFO and does not indicate a functional issue, provided the packet completes correctly during the last cycle when out_valid is asserted. In AVST, the out_valid qualifies every other source output. The sink should only sample data, sop, eop, empty, etc., on cycles where valid (and ready, for a transfer) are asserted. When out_valid is low, out_eop is considered a don’t-care and may appear as X(red) in simulation.
Regards,
Richard Tan - RichardT_altera
Could you share the .qar design and testbench so I can reproduce the simulation waveform and perform further analysis?
Regards,
Richard Tan 
opexsysHi Richard,
Thank you for the response! The .qar designs and testbenches are included in this reply as a zip file.- opexsys
Thank for the explanation.
- RichardT_altera
You're welcome.
I'm happy to help.
