AVST FIFO and AVST Demultiplexer IP Simulation Behavior

Sorry for the delay.
1) Yes, this behavior is normal. The endofpacket signal is only meaningful when valid is asserted. When valid is deasserted, all output signals are considered don’t-care and may retain their previous values. In this case, the demultiplexer IP is simply holding the last value of endofpacket.

2) Yes, this behavior is also normal in simulation for the Avalon Streaming Single Clock FIFO and does not indicate a functional issue, provided the packet completes correctly during the last cycle when out_valid is asserted. In AVST, the out_valid qualifies every other source output. The sink should only sample data, sop, eop, empty, etc., on cycles where valid (and ready, for a transfer) are asserted. When out_valid is low, out_eop is considered a don’t-care and may appear as X(red) in simulation.

Regards,
Richard Tan