Forum Discussion
Adithiya_R
New Contributor
New ContributorIntel P-tile HIP clock not visible during timing analysis "all clock report"
Hi Everyone, We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logi...
Adithiya_RNew Contributor
New ContributorHi
PLD_CLOCK_FREQ will eventually reflect as coreclkout_hip, is it ?
if this is the setting , then user_logic ( bar_access fails ) ---- So suspecting this freq_change is causing some issues , for which we need timing_analysis wrt coreclkout_hip or user_clk
And sof is working perfect for Gen3 and not working for gen4 where PLD_CLK_FREQ is the only change. why is that ?
