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Adithiya_R's avatar
Adithiya_R
Icon for New Contributor rankNew Contributor
1 year ago

Intel P-tile HIP clock not visible during timing analysis "all clock report"

Hi Everyone, We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logi...
Pcie
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Please make sure the output clock coreclkout_hip being used internally like feeding to other logic. Make sure there's fanout or usage internally. May I know possible provide the design for taking a look?


Thanks,

Regards,

Sheng