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Honored Contributor
Honored ContributorHow to implement DE0 SDRAM as 2-port RAM
I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one more layer above that which implements this controller as a 2-port RAM entity. It seems like overkill to use QSYS with NiosII though, plus I'm not very familiar with it. What's resource will help me implement this controller as a 2-port RAM entity in the simplest way possible?
entity sdr_sdram is
generic(
ASIZE : integer := 23;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 9;
BANKSIZE : integer := 2;
ROWSTART : integer := 9;
COLSTART : integer := 0;
BANKSTART : integer := 20
);
port(
CLK : in std_logic; --System Clock
RESET_N : in std_logic; --System Reset
ADDR : in std_logic_vector(ASIZE - 1 downto 0); --Address for controller requests
CMD : in std_logic_vector(2 downto 0); --Controller command
CMDACK : out std_logic; --Controller command acknowledgement
DATAIN : in std_logic_vector(DSIZE - 1 downto 0); --Data input
DATAOUT : out std_logic_vector(DSIZE - 1 downto 0); --Data output
DM : in std_logic_vector(DSIZE / 8 - 1 downto 0); --Data mask input
SA : out std_logic_vector(11 downto 0); --SDRAM address output
BA : out std_logic_vector(1 downto 0); --SDRAM bank address
CS_N : out std_logic_vector(1 downto 0); --SDRAM Chip Selects
CKE : out std_logic; --SDRAM clock enable
RAS_N : out std_logic; --SDRAM Row address Strobe
CAS_N : out std_logic; --SDRAM Column address Strobe
WE_N : out std_logic; --SDRAM write enable
DQ : inout std_logic_vector(DSIZE - 1 downto 0); --SDRAM data bus
DQM : out std_logic_vector(DSIZE / 8 - 1 downto 0) --SDRAM data mask lines
);
end sdr_sdram;
Inst_frame_buffer : entity work.sdram_wrapper_frame_buffer PORT MAP(
rdaddress => rdaddress, -- IN std_logic_vector(18 downto 0);
rdclock => clk_vga, -- IN std_logic;
q => rddata, -- OUT std_logic_vector(11 downto 0)
wrclock => camera_pclk, -- IN std_logic;
wraddress => wraddress, -- IN std_logic_vector(18 downto 0);
data => wrdata, -- IN std_logic_vector(11 downto 0);
wren => wren -- IN std_logic;
);
