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The SDRAM size is different for the DE0-nano vs my regular DE0 board.
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You can start Qsys and modify the SDRAM parameters.
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Can I hire someone to make a quick VHDL wrapper for the Altera SDRAM controller I have as a 1-Port RAM entity that has multiple-master access functionality?
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Its not the SDRAM that provides the multiple master functionality, its the fabric created by Qsys. When you connect two masters to a slave, the fabric adds arbitration logic.
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I don't mind doing it with Qsys either but I would need a tutorial that doesn't use a JTAG interface or NiosII. It seems odd that this is such a hard thing to find..
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A Qsys system needs at least one master (otherwise there is no point in creating the system), and the two easiest ones to demonstrate in a tutorial are NIOS II or JTAG.
What are you trying to do that is not supported by existing components. Perhaps if you could explain what you are trying to do, people on the forum can suggest options for you to look into.
Cheers,
Dave
Honored Contributor
