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Altera_Forum
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10 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I checked that out. I don't where to begin to modify it to be what I need it to be though. Ideally it would all be in VHDL, no JTAG, no TCL, and the SDRAM size is different for the DE0-nano vs my regular DE0 board. Can I hire someone to make a quick VHDL wrapper for the Altera SDRAM controller I have as a 1-Port RAM entity that has multiple-master access functionality? I don't mind doing it with Qsys either but I would need a tutorial that doesn't use a JTAG interface or NiosII. It seems odd that this is such a hard thing to find..