Honored Contributor
Honored Contributor"simple" is relative.
If your components were re-written to use standard Avalon-MM and Avalon-ST interfaces, then you could "simply" create a Qsys system. The SDRAM controller interface is that of an Avalon-MM slave. I'm sure you can create an instance all by itself, but that would not provide the dual-ported interface you want. You could create an Avalon-MM system with the SDRAM controller and two exported Avalon-MM master interfaces, so that Qsys will create the arbitration logic, and then you can interface to the two Avalon-MM master interfaces exported to the top-level. But if you have to interface to two Avalon-MM masters at the top-level, you may as well just create Avalon-MM master components for your existing code, and drop them into a Qsys system. Basically it comes down to how much time you want to waste "fighting" the tools. Altera and Xilinx have decided to use standardized bus interfaces (Avalon-MM, Avalon-ST, AXI4, AXI4-Lite, AXI4-Stream, etc) so that they can give their end-users system building tools like Qsys. If you have custom logic, then often its easier to modify the code to make it use a standard interface. Cheers, Dave
