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ok. 1. Which direction should I go in, pure VHDL, or a QSYS-based system?
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It depends on how interconnected your components are, and how reuseable your code is, and how much Altera IP you plan on using.
Many systems can be separated into a "Control Plane" and a "Data Plane", where the "Data Plane" are your high-speed processing blocks (the reason you chose an FPGA), and the "Control Plane" is the part where you configure the data plane, eg., program packet sizes, monitor statistics, set coefficients (stuff that changes on a slower timescale).
As soon as you try and use some Altera IP, there is a pretty good chance to have to use the Avalon-ST or Avalon-MM component interface. At that point you need to decide whether to make your custom components work within the Qsys environment, or whether they'll sit "outside" a Qsys design containing all the Altera IP.
The Avalon-MM/ST interfaces are described in the Avalon Interface Standard and in the Verification IP Users Guide.
If you were going to target both Altera and Xilinx devices, then you should look at the ARM AMBA AXI4 standard interfaces.
Cheers,
Dave
Honored Contributor
