How to implement DE0 SDRAM as 2-port RAM

I guess, but the way I originally formed the question removes the need to know the details of the project. It keeps it simple. I just need to use SDRAM as if it was a simple 1-port ram. I already have the controller and the entities the controller instantiates which is written by Altera and designed for the SDRAM chip on the development boards, I just need help with the next layer which does the job of making the interface even simpler. It would just have something like clock, address, ready, write/read, and data. Do you see what I mean? It's hard to believe that using SDRAM as a simple RAM component isn't a very common thing people do regardless of the application. Is there either a QSYS tutorial just for making SDRAM into a simpler RAM component or an SDRAM controller wrapper that already exists, or that I can hire someone to write? This has got to be so easy for someone more experienced than myself..