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Altera_Forum
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10 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

ok. 1. Which direction should I go in, pure VHDL, or a QSYS-based system? In the really big picture I am porting over a fairly large computer vision application. This is going to get a lot bigger and more complicated than just storing a frame in ram and sending it back out again to a VGA monitor. That's nothing. Eventually motion detection will be implemented which will be followed by a lot of other layers of custom image processing logic on top of that. RAM and FLASH (or an SD CARD) will also have to be used. I also want to do the pixel comparisons in parallel of course, that being one of the main reasons for using an FPGA. 2. So knowing that, does sticking to a purely VHDL system seem totally ridiculous?

3. Will NiosII have to be involved in a project like this? If so, why?

4. I have read a little about Avalon-MM and Avalon-ST interfaces but is there a guide that you know of for modifying the code to make it use a standard interface?