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Altera_Forum
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11 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Alright. It seems like QSYS is for projects where the developer wants to use a NiosII processor or JTAG interface. I want to focus on making the wrapper for the SDRAM controller. It is likely only an hour or less of work for someone more experienced than myself. What is the next step in getting assistance in developing this wrapper?