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What's resource will help me implement this controller as a 2-port RAM entity in the simplest way possible?
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The SDRAM interface has only one port, so you can only use it as 1-port RAM.
What you are probably after is multiple-master access to the common resource. This is possible if the two devices (masters) access the SDRAM at a rate that is slower than the SDRAM interface maximum performance. Eg., two devices accessing 100MHz SDRAM at an effective data rate of say 10MHz would work fine.
Multi-master arbitration of the SDRAM interface would be done automatically for you if you use Qsys.
Here's an SDRAM example to get you started.
http://www.alteraforum.com/forum/showthread.php?t=45927 This does not use NIOS II. It uses the JTAG interface to allow your PC to access the SDRAM.
Cheers,
Dave
Honored Contributor
