HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi Rong,

Hope you and others at Intel are well into the new year

Its been a while since the last update on this case.

Can you please provide a status, just to assume me that the case is still active ?

Regards,

M_DK_FPGA

Hi Rong,

Thanks for getting back to this question.

On the December 18th 2024 I made a pretty elaborate description for the possible contradictions in the documentation, and asked:

Question: Can you please revisit this question, based on the above information, and clarify what is actually supported, and what part of the documentation that is incorrect.

On the December 22nd 2024 you reassuringly wrote "Please allow some more time to confirm this issue.".

The answer today as "These could be doc errors. Some limitations not mentioned clearly." does not clarify what is actually supported, and does not describe what part of the documentation that is incorrect.

Can you please revisit my description and question from December 18th 2024, so we can determine how the HDMI Intel FPGA IP can be used, or let me know who to contact to get this question resolved.

Thanks in advance.

Regards
M_DK_FPGA

Hi Rong,

Thanks for the suggested workaround.

I tried it by generating the example design for HDMI loop from Rx to Tx.

From this design I took the HDMI Rx core named "intel_hdmi_rx_core_0" and copied the directory and ip file to my own project.

The core is configured with enabled "Support Auxiliary" and enabled "Support Deep Color", thus 48 bit pixel data, where my design from 12-15-2024 only has 24 bit pixel data.

So after changing my original design from 24 to 48 bit pixel data, and using the HDMI Rx core named "intel_hdmi_rx_core_0", Quartus could successfully run the full build.

To modify the core to match our required configuration, I disabled "Support Auxiliary" and disable "Support Deep Color", and regenerated the core.

Then I edited the design to use 24 bit pixel data, to match the disabled "Support Deep Color", and ran Quartus build.

This resulted in the Quartus error in "Analysis & Synthesis":

Error(13224): Verilog HDL or VHDL error at intel_cv2axi_remap.sv(154): index ** is out of range [**:**] for '**' 
Error: Failed to elaborate design: 
Error: Flow failed: Errors generated during elaboration 

The file intel_cv2axi_remap.sv is part of the HDMI Rx core and contains encrypted code, so I can't determine the reason for the error.

The suggested workaround with use of the example design, is thus only applicable if the HDMI Rx core can be used without core rebuild, making the workaround of limited use. Also, I expect the core will also break if rebuild is required at upgrade to a future Quartus Pro version, thus effectively inhibiting such upgrade.

So, it appears there is a problem with the HDMI Rx core build system, and I suppose that problem is also the reason for suggesting the workaround using the example design, instead of just advising use of the HDMI Rx core build system.

Question: Do you have any suggestion for fixing the above problem in file intel_cv2axi_remap.sv, or any other suggestions for how to generate the HDMI Rx core in the required configuration ?

Thanks in advance.

Regards
M_DK_FPGA

Hi Rong,

Thanks for replying so quickly.

I have attached the Quartus project with the failing core in the attached file "proj_24_3_0_212_hdmi_rx_core_modified.qar" for the problem I reported yesterday.

Please let me know and elaborate if you expect me to file an "IPS", as you requested.

Though it maybe interesting to debug the problem reported yesterday, based on the attached file "proj_24_3_0_212_hdmi_rx_core_modified.qar", I fear that we are getting out on a deroute here, and not really addressing the original question posted for more than a month ago.

Also, it appears that I get few specific answers or useful suggestions, even based on the quite elaborate replies and specific questions I post.

So may I kindly suggest, that you backtrack to the original report and maybe reply at 12-18-2024 in this support request, and see if you or others at Intel can address the original problem, since it appears as there is a problem with the HDMI Rx core generation tool.

Otherwise, please let me know how if you have other suggestion for addressing this support question more effectively.

Thanks in advance.

Regards
M_DK_FPGA

Hi Rong,

Thanks for the link.

I have applied, and will let you know when application is confirmed, and I have then posted the question.

Regards
M_DK_FPGA

Hi @M_DK_FPGA ,

I tried it by generating the example design for HDMI loop from Rx to Tx.

From this design I took the HDMI Rx core named "intel_hdmi_rx_core_0" and copied the directory and ip file to my own project.
>> I assume you try to generate the design example as suggested by Rong in the past reply right ?
>> Do you try to run compilation without any modification ? is it work ?

On the December 18th 2024 I made a pretty elaborate description for the possible contradictions in the documentation, and asked:

Question: Can you please revisit this question, based on the above information, and clarify what is actually supported, and what part of the documentation that is incorrect.
>> May I know which device that currently you are using ?

>> mentioned from this link: https://www.intel.com/content/www/us/en/docs/programmable/732147/22-3-1-0-1/hdmi-phy-overview.html

Error(13224): Verilog HDL or VHDL error at intel_cv2axi_remap.sv(154): index ** is out of range [**:**] for '**

>> just to check with you, if you remain 48 bit pixel data do you still able to see the same error ?

Meanwhile, I will check the .qar file attach by you, please allow me to have sometime on that.

Regards,
Wincent_Altera