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Re: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thank you for your thoughtful response and your generous offer of future support—it is truly appreciated. I will accept the suggested workaround as the solution and will post a new question in this forum if any further issues arise. Best regards, M_DK_FPGA1.8KViews0likes0CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, OK, thanks for the suggested workaround, and I see the point that the AUX and Deep Color features can be disabled by just tying the interface to constants, whereby synthesis will remove the idle design part. However, I still assume that disabling the features in the interface should not break synthesis, nor make output in-stable (blank most of the time), which may be relevant only to other users of the core, now that you have pointed out a possible workaround. Please feel free to close the case if you think it is covered. Regards M_DK_FPGA1.8KViews0likes2CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thanks for getting back to this so quickly, and it is reassuring that you see the same tool behaviour. It sounds good you will elevate the support case, if you concurs that there may be a problem in the HDMI core IP. I am looking forward to any further updates. Regards M_DK_FPGA2KViews0likes4CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thanks for your feedback, and suggestion about raising an IPS case. As described previously, then Intel rejected my request for an IPS account, so to make an IPS case I have to go through our FAE, who have offered the possibility through some shared IPS account. However, I am reluctant to draw on the good will of our FAE, just to ask the same question and start yet another lengthy support case in another forum. During this support case I have provided substantial material that indicates a problem in the HDMI core IP, starting with the initial posting more than 11 weeks ago, but there is no indication that support ever attempted to reproduce these problem, through it would only require synthesis of the uploaded archives, to acknowledge the problem. Instead I have been offered workarounds, that I dutifully have attempted, and provided replies in a day or two, but when I have pointed out problems with the workaround, my substantial issues and questions have not been addressed. So as a small company we have been forced to search for another path through with the HDMI core IP, since relaying on support bears the risk of jeopardizing the project. Regards M_DK_FPGA2.1KViews0likes6CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thanks for the project file .qar. The HDMI Rx IP shows that the Video Protocol is None, as you can seen in the attached image. May I suggest that you try to unpack the qar file you attached, and check the actual IP setting. You can also just search for VIDEO_PROTOCOL in the files, where you in file ^/devkit2/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.xml will find <parameter name="VIDEO_PROTOCOL" value="none" />. Please also take a look at the originally generated code, where I in my previous answer described the mismatch between config parameters PIXELS_PER_CLOCK and SYMBOLS_PER_CLOCK. Also you could try just to run the synthesis of the originally attached qar file, which will shown the problem. That should be straight forward to do. Thanks for the offer for a Teams Call For now I think we have enough technical issues to resolve, so until the above is addressed I would not think a Teams Call is required. Regards M_DK_FPGA2.3KViews0likes10CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thanks for the project file .qar. I unpacked the files, and looked at the HDMI IP Rx and Tx cores. Searching for VIDEO_PROTOCOL shows that the setting is "none" for clocked video, and not "vvp_full" for "AXIS-VVP Full"; relevant files are: ^/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.html and .xml ^/hdmi_0_example_design/rtl/hdmi_tx/hdmi_tx/hdmi_tx.html and .xml The design also shows it, since the HDMI IP Rx and Tx PHYs are not used as would require AXIS-VVP Full, but the transceivers for HDMI are made using GXB blocks directly. May I suggest that you take a look at the original question from December 15 2024, and try to generate the HDMI Core with: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) The generated design is also attached as a file .qar with the original question. Simply by code inspection of the generated hdmi_rx_core_altera_hdmi_1975_ozylggi.v file, it is possible to see that there is problem with the design. The module hdmi_rx_core_altera_hdmi_1975_ozylggi is used in file hdmi_rx_core.vhd at lines 192 forward through a component with configuration as: ... hdmi_0 : component hdmi_rx_core_altera_hdmi_1975_ozylggi_cmp generic map ( FAMILY => "Arria 10", SYMBOLS_PER_CLOCK => 2, PIXELS_PER_CLOCK => 8, ... The module in file hdmi_rx_core_altera_hdmi_1975_ozylggi.v has code: ... wire [SYMBOLS_PER_CLOCK - 1 : 0] cv_vid_de; ... for (p=0; p<PIXELS_PER_CLOCK; p=p+1) begin: vid_data_p ... if(cv_vid_de[p] && (vid_valid == 1'b1)) begin ... So loop variable p is in range 0 to PIXELS_PER_CLOCK - 1 = 8 - 1 = 7, but wire cv_vid_de is only defined with range 0 to SYMBOLS_PER_CLOCK - 1 = 2 - 1 = 1. During synthesis, Quartus tries to access p[2], that is out of range, thus giving the error meassage: Error(13224): Verilog HDL or VHDL error at hdmi_rx_core_altera_hdmi_1975_ozylggi.v(771): index 2 is out of range [1:0] for 'cv_vid_de' This problem can be confirmed by code inspection, thus without any pin placement or other synthesis. Have you tried to recreate the original problem that I reported, showing the above problem in the code ? Regards M_DK_FPGA2.2KViews0likes0CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thanks for the project file .qar. I unpacked the files, and looked at the HDMI IP Rx and Tx cores. Searching for VIDEO_PROTOCOL shows that the setting is "none" for clocked video, and not "vvp_full" for "AXIS-VVP Full"; relevant files are: ^/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.html and .xml ^/hdmi_0_example_design/rtl/hdmi_tx/hdmi_tx/hdmi_tx.html and .xml The design also shows it, since the HDMI IP Rx and Tx PHYs are not used as would require AXIS-VVP Full, but the transceivers for HDMI are made using GXB blocks directly. May I suggest that you take a look at the original question from December 15 2024, and try to generate the HDMI Core with: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) The generated design is also attached as a file .qar with the original question. Simply by code inspection of the generated hdmi_rx_core_altera_hdmi_1975_ozylggi.v file, it is possible to see that there is problem with the design. The module hdmi_rx_core_altera_hdmi_1975_ozylggi is used in file hdmi_rx_core.vhd at lines 192 forward through a component with configuration as: ... hdmi_0 : component hdmi_rx_core_altera_hdmi_1975_ozylggi_cmp generic map ( FAMILY => "Arria 10", SYMBOLS_PER_CLOCK => 2, PIXELS_PER_CLOCK => 8, ... The module in file hdmi_rx_core_altera_hdmi_1975_ozylggi.v has code: ... wire [SYMBOLS_PER_CLOCK - 1 : 0] cv_vid_de; ... for (p=0; p<PIXELS_PER_CLOCK; p=p+1) begin: vid_data_p ... if(cv_vid_de[p] && (vid_valid == 1'b1)) begin ... So loop variable p is in range 0 to PIXELS_PER_CLOCK - 1 = 8 - 1 = 7, but wire cv_vid_de is only defined with range 0 to SYMBOLS_PER_CLOCK - 1 = 2 - 1 = 1. During synthesis, Quartus tries to access p[2], that is out of range, thus giving the error meassage: Error(13224): Verilog HDL or VHDL error at hdmi_rx_core_altera_hdmi_1975_ozylggi.v(771): index 2 is out of range [1:0] for 'cv_vid_de' This problem can be confirmed by code inspection, thus without any pin placement or other synthesis. Have you tried to recreate the original problem that I reported, showing the above problem in the code ? Regards M_DK_FPGA2.3KViews0likes1CommentRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, The .hex file used for EDID I used was just the one provided in the example, since the problem I see with the IP core does not depend on EDID. However, I have attached the file anyway (renamed to .txt to allow attach). Regarding the lack of pin placement, then I think it does not effect the problems reported in the encrypted IP cores and the problem with mismatch of vector size in the Verilog IP core. Pin placement was not used in any of the compiles designs, and in the example with correct vector size in the Verilog IP core, the Quartus did automatic pin placement (also for transceivers) as it typically does quite effectively. Regards M_DK_FPGA2.3KViews0likes2CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Wincent_Altera, Thanks for looking into this case. Initially I would like to note, that it may be worth starting with my initial issue, where I experience that the IP core build directly from Quartus does not synthesize. The project is attached with the original posting from 12-15-2024. I think it is very surprising that the IP build right from Quartus does not synthesize, and if my experience is correct, then it may point to a problem in Quartus. Below I have put feedback/answers to your 3 questions. >> I assume you try to generate the design example as suggested by Rong in the past reply right ? >> Do you try to run compilation without any modification ? is it work ? The design was compiled unmodified, except for changes at the interface that was made 48 bit instead of 24 bit, in order to match enable of "Support Deep Color". >> May I know which device that currently you are using ? Arria 10 GX (10AX032H3F34E2SG). >> just to check with you, if you remain 48 bit pixel data do you still able to see the same error ? After disable of "Support Deep Color", then the interface is only 24 bit, so in order to match the width I changed to 24 bits. Using 48 bit externally on a 24 bit interface does not is a mismatch of interface width. With respect to the reported error, then that is in internal Intel IP design, that is not directly connected to the external interface where I change the interface width. The external interface width does therefore not affect the internal IP design, thus nor the reason for the error. The failing design was attached in my reply at 01-16-2025, so you are able to inspect and try it from there. Regards M_DK_FPGA2.7KViews0likes6CommentsRe: HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi Rong, Thanks for getting back to this question, though a reply time of 25 days is quite long. We have tried to get support through our local representative, but we are not eligible for an IPS account. However, the question about an IPS account should not derail the support effort here, unless community support is not able to address the question about whey the HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro. If community support is unable to address the support question, then please close the question. Regards M_DK_FPGA2.8KViews0likes8Comments