Forum Discussion
Occasional ContributorHDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi @M_DK_FPGA ,
I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.Currently AXI Bridge is setting to 16BPS (16x3 48bits).
If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
Detail about the implementation you may refer to- HDMI user guide 5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV)
- Intel AXI Streaming Video Protocol Specification: 2.2.10. Packing RGB444 onto an RGB888 Interface
Hope that able to help you to move a step forward, let me know if further clarification is needed.
Regards,
Wincent_Altera
Regular ContributorHi @M_DK_FPGA ,
Another issue that I found based on your .qar file is your pin assignment is totally empty.
it could be lead to the error you are seeing.
You may refer to https://www.intel.com/content/www/us/en/docs/programmable/683814/current/intel-arria-10-gx-gt-and-sx-device-family.html
https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html
To assign it, I will try to generate a design based on A10 GX devkit with AXIS-VVP full as per your reference once I get your .hex file.
Regards,
Wincent_Altera
Occasional ContributorHi Wincent_Altera,
The .hex file used for EDID I used was just the one provided in the example, since the problem I see with the IP core does not depend on EDID. However, I have attached the file anyway (renamed to .txt to allow attach).
Regarding the lack of pin placement, then I think it does not effect the problems reported in the encrypted IP cores and the problem with mismatch of vector size in the Verilog IP core. Pin placement was not used in any of the compiles designs, and in the example with correct vector size in the Verilog IP core, the Quartus did automatic pin placement (also for transceivers) as it typically does quite effectively.
Regards
M_DK_FPGA
- Wincent_Altera
Hi @M_DK_FPGA ,
I was able to generate and perform 100 % compilation by referring your .ip setup and EDID.hex file using AXIS-VVP Full in Arria 10 GX devkit. I attach the .qar here.Can you please try this, you may copy the .qsf file into your own design.
Regards,
Wincent_Altera - M_DK_FPGA
Hi Wincent_Altera,
Thanks for the project file .qar.
I unpacked the files, and looked at the HDMI IP Rx and Tx cores.
Searching for VIDEO_PROTOCOL shows that the setting is "none" for clocked video, and not "vvp_full" for "AXIS-VVP Full"; relevant files are:
- ^/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.html and .xml
- ^/hdmi_0_example_design/rtl/hdmi_tx/hdmi_tx/hdmi_tx.html and .xml
The design also shows it, since the HDMI IP Rx and Tx PHYs are not used as would require AXIS-VVP Full, but the transceivers for HDMI are made using GXB blocks directly.
May I suggest that you take a look at the original question from December 15 2024, and try to generate the HDMI Core with:
- Direction: Receiver
- Enable Active Video Protocol: AXIS-VVP Full
- Support FRL: Untick (disabled)The generated design is also attached as a file .qar with the original question.
Simply by code inspection of the generated hdmi_rx_core_altera_hdmi_1975_ozylggi.v file, it is possible to see that there is problem with the design.
The module hdmi_rx_core_altera_hdmi_1975_ozylggi is used in file hdmi_rx_core.vhd at lines 192 forward through a component with configuration as:
...
hdmi_0 : component hdmi_rx_core_altera_hdmi_1975_ozylggi_cmp
generic map (
FAMILY => "Arria 10",
SYMBOLS_PER_CLOCK => 2,
PIXELS_PER_CLOCK => 8,
...
The module in file hdmi_rx_core_altera_hdmi_1975_ozylggi.v has code:
...
wire [SYMBOLS_PER_CLOCK - 1 : 0] cv_vid_de;
...
for (p=0; p<PIXELS_PER_CLOCK; p=p+1) begin: vid_data_p
...
if(cv_vid_de[p] && (vid_valid == 1'b1)) begin
...So loop variable p is in range 0 to PIXELS_PER_CLOCK - 1 = 8 - 1 = 7, but wire cv_vid_de is only defined with range 0 to SYMBOLS_PER_CLOCK - 1 = 2 - 1 = 1.
During synthesis, Quartus tries to access p[2], that is out of range, thus giving the error meassage:
Error(13224): Verilog HDL or VHDL error at hdmi_rx_core_altera_hdmi_1975_ozylggi.v(771): index 2 is out of range [1:0] for 'cv_vid_de'This problem can be confirmed by code inspection, thus without any pin placement or other synthesis.
Have you tried to recreate the original problem that I reported, showing the above problem in the code ?
Regards
M_DK_FPGA
