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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
12 months ago
Solved

HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Th...
Video
  • Wincent_Altera's avatar
    Wincent_Altera
    9 months ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
9 months ago

Hi @M_DK_FPGA ,


First and foremost, I would sincerely apologies that the workaround take unexpected delivery time.
Please believe that, I am trying my best to ensure you and all of my client success.


Feel free to try out those workaround, if you facing any issue or anything need to be further clarified, please post a new forum.
If you need specific my support, you may point out my name "Wincent" in the description, It will be pleasure there to support you again. Hope this help to accelerate your current project progress.

Regards,
Wincent_Altera

M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi Wincent_Altera,

Thank you for your thoughtful response and your generous offer of future support—it is truly appreciated.

I will accept the suggested workaround as the solution and will post a new question in this forum if any further issues arise.

Best regards,
M_DK_FPGA