Forum Discussion
Occasional ContributorHDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi @M_DK_FPGA ,
I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.Currently AXI Bridge is setting to 16BPS (16x3 48bits).
If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
Detail about the implementation you may refer to- HDMI user guide 5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV)
- Intel AXI Streaming Video Protocol Specification: 2.2.10. Packing RGB444 onto an RGB888 Interface
Hope that able to help you to move a step forward, let me know if further clarification is needed.
Regards,
Wincent_Altera
ContributorHi M_DK_FPGA,
After my above reply with question, I got a mail asking "Did it solve your problem?".
-Thanks for the feedback. I'm still checking answers for your questions. Not sure why system sent you that.
Please allow some more time to confirm this issue.
Regards,
Rong
M_DK_FPGAHi Rong,
Hope you and others at Intel are well into the new year
Its been a while since the last update on this case.
Can you please provide a status, just to assume me that the case is still active ?
Regards,
M_DK_FPGA
