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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Th...
Video
  • Wincent_Altera's avatar
    Wincent_Altera
    1 year ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

Hi,

Your modification may need further check and investigation in order to meet your requirements. Please file an IPS for this.


Thanks,

Rong


M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Rong,

Thanks for replying so quickly.

I have attached the Quartus project with the failing core in the attached file "proj_24_3_0_212_hdmi_rx_core_modified.qar" for the problem I reported yesterday.

Please let me know and elaborate if you expect me to file an "IPS", as you requested.


Though it maybe interesting to debug the problem reported yesterday, based on the attached file "proj_24_3_0_212_hdmi_rx_core_modified.qar", I fear that we are getting out on a deroute here, and not really addressing the original question posted for more than a month ago.

Also, it appears that I get few specific answers or useful suggestions, even based on the quite elaborate replies and specific questions I post.

So may I kindly suggest, that you backtrack to the original report and maybe reply at 12-18-2024 in this support request, and see if you or others at Intel can address the original problem, since it appears as there is a problem with the HDMI Rx core generation tool.

Otherwise, please let me know how if you have other suggestion for addressing this support question more effectively.


Thanks in advance.

Regards
M_DK_FPGA