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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Th...
Video
  • Wincent_Altera's avatar
    Wincent_Altera
    1 year ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Rong,

Thanks for the link.

I have applied, and will let you know when application is confirmed, and I have then posted the question.

Regards
M_DK_FPGA

M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Rong,

My application for IPS was declined based on the same account as used here.

Please let me know if you have any suggestions or resolution regarding my IPS application.

Also please address this support can here, if possible, since I see no other possibility for now.

Thanks in advance.

Regards
M_DK_FPGA