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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Th...
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  • Wincent_Altera's avatar
    Wincent_Altera
    1 year ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi @M_DK_FPGA ,

I tried it by generating the example design for HDMI loop from Rx to Tx.

From this design I took the HDMI Rx core named "intel_hdmi_rx_core_0" and copied the directory and ip file to my own project.
>> I assume you try to generate the design example as suggested by Rong in the past reply right ?
>> Do you try to run compilation without any modification ? is it work ?

On the December 18th 2024 I made a pretty elaborate description for the possible contradictions in the documentation, and asked:

Question: Can you please revisit this question, based on the above information, and clarify what is actually supported, and what part of the documentation that is incorrect.
>> May I know which device that currently you are using ?

>> mentioned from this link: https://www.intel.com/content/www/us/en/docs/programmable/732147/22-3-1-0-1/hdmi-phy-overview.html

"You must instantiate the HDMI core with Support FRL = 0 (for Intel® Arria® 10) or Support FRL = 1 (for Intel® Agilex™ F-tile) and Enable Active Video Protocol = AXIS-VVP Full to use Intel HDMI TX or RX PHY IP."

Error(13224): Verilog HDL or VHDL error at intel_cv2axi_remap.sv(154): index ** is out of range [**:**] for '**

>> just to check with you, if you remain 48 bit pixel data do you still able to see the same error ?

Meanwhile, I will check the .qar file attach by you, please allow me to have sometime on that.

Regards,
Wincent_Altera

M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Wincent_Altera,

Thanks for looking into this case.

Initially I would like to note, that it may be worth starting with my initial issue, where I experience that the IP core build directly from Quartus does not synthesize. The project is attached with the original posting from 12-15-2024. I think it is very surprising that the IP build right from Quartus does not synthesize, and if my experience is correct, then it may point to a problem in Quartus.

Below I have put feedback/answers to your 3 questions.

>> I assume you try to generate the design example as suggested by Rong in the past reply right ?
>> Do you try to run compilation without any modification ? is it work ?

The design was compiled unmodified, except for changes at the interface that was made 48 bit instead of 24 bit, in order to match enable of "Support Deep Color".

>> May I know which device that currently you are using ?

Arria 10 GX (10AX032H3F34E2SG).

>> just to check with you, if you remain 48 bit pixel data do you still able to see the same error ?

After disable of "Support Deep Color", then the interface is only 24 bit, so in order to match the width I changed to 24 bits. Using 48 bit externally on a 24 bit interface does not is a mismatch of interface width.

With respect to the reported error, then that is in internal Intel IP design, that is not directly connected to the external interface where I change the interface width. The external interface width does therefore not affect the internal IP design, thus nor the reason for the error.

The failing design was attached in my reply at ‎01-16-2025, so you are able to inspect and try it from there.

Regards
M_DK_FPGA