Forum Discussion
Occasional ContributorHDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi @M_DK_FPGA ,
I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.Currently AXI Bridge is setting to 16BPS (16x3 48bits).
If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
Detail about the implementation you may refer to- HDMI user guide 5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV)
- Intel AXI Streaming Video Protocol Specification: 2.2.10. Packing RGB444 onto an RGB888 Interface
Hope that able to help you to move a step forward, let me know if further clarification is needed.
Regards,
Wincent_Altera
ContributorHi,
If you really want AXIS-VVP example, you can generate it from HDMI PHY IP. The example enables AXIS-VVP by default.
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10...
Regards,
Rong
Occasional ContributorHi Rong,
Thanks for the suggested workaround.
I tried it by generating the example design for HDMI loop from Rx to Tx.
From this design I took the HDMI Rx core named "intel_hdmi_rx_core_0" and copied the directory and ip file to my own project.
The core is configured with enabled "Support Auxiliary" and enabled "Support Deep Color", thus 48 bit pixel data, where my design from 12-15-2024 only has 24 bit pixel data.
So after changing my original design from 24 to 48 bit pixel data, and using the HDMI Rx core named "intel_hdmi_rx_core_0", Quartus could successfully run the full build.
To modify the core to match our required configuration, I disabled "Support Auxiliary" and disable "Support Deep Color", and regenerated the core.
Then I edited the design to use 24 bit pixel data, to match the disabled "Support Deep Color", and ran Quartus build.
This resulted in the Quartus error in "Analysis & Synthesis":
Error(13224): Verilog HDL or VHDL error at intel_cv2axi_remap.sv(154): index ** is out of range [**:**] for '**'
Error: Failed to elaborate design:
Error: Flow failed: Errors generated during elaboration
The file intel_cv2axi_remap.sv is part of the HDMI Rx core and contains encrypted code, so I can't determine the reason for the error.
The suggested workaround with use of the example design, is thus only applicable if the HDMI Rx core can be used without core rebuild, making the workaround of limited use. Also, I expect the core will also break if rebuild is required at upgrade to a future Quartus Pro version, thus effectively inhibiting such upgrade.
So, it appears there is a problem with the HDMI Rx core build system, and I suppose that problem is also the reason for suggesting the workaround using the example design, instead of just advising use of the HDMI Rx core build system.
Question: Do you have any suggestion for fixing the above problem in file intel_cv2axi_remap.sv, or any other suggestions for how to generate the HDMI Rx core in the required configuration ?
Thanks in advance.
Regards
M_DK_FPGA
