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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Th...
Video
  • Wincent_Altera's avatar
    Wincent_Altera
    1 year ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

Hi,

These could be doc errors. Some limitations not mentioned clearly.


Regards,

Rong


M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Rong,

Thanks for getting back to this question.

On the December 18th 2024 I made a pretty elaborate description for the possible contradictions in the documentation, and asked:

Question: Can you please revisit this question, based on the above information, and clarify what is actually supported, and what part of the documentation that is incorrect.


On the December 22nd 2024 you reassuringly wrote "Please allow some more time to confirm this issue.".

The answer today as "These could be doc errors. Some limitations not mentioned clearly." does not clarify what is actually supported, and does not describe what part of the documentation that is incorrect.

Can you please revisit my description and question from December 18th 2024, so we can determine how the HDMI Intel FPGA IP can be used, or let me know who to contact to get this question resolved.

Thanks in advance.

Regards
M_DK_FPGA