A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi @Sijith,

Yes, I obtained the .qsys file from the attached ModifiedDesign.zip in the previous thread. May I know have you tried to run the Signal Tap to check the DDR? What is the observation?

The objective of generating the EMIF example design is to observe the connections on how the DDR store the incoming data because your qsys connection seemed off.

Since you have the next step which is using an external source to replace the counter for input data, I'd suggest you to directly go to this step. And then we can debug from there. Because it's not sure if we replace the counter with the external source, it might create other issues or not.

But if you want to use the counter to generate data and stream the data to DDR4 through FIFO, I think the counter should connect to the DDR4.

From the unmodified example design which you've run successfully, it already performed the DMA read and write operations to DDR4.

May I know what is protocol that you used to feed the data stream to FIFO and to DDR?

Thanks.

Best Regards,

VenTing_Intel

Hi,

Thank you very much. Did not finished run SignalTap yet. Will update you very soon the result.

For feeding data from external source, I have to get the design and to develop data transfer design (QSFP+ to the FIFO then to DMA example design) strategy. So thought using counter to test the data transfer from FIFO to DMA transfer example design will be a quick validation I can do first.

In this reply message above (

community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1560274#M28411 )

He was mentioning about the absence of "valid data path from fifo to dma_wr_master ", this need only when we connect the FIFO to DMA, right? Or am I missing something?

The correct way to connect the FIFO to DDR4 is though the EMIF, right?

I have used the Avalon Streaming from counter to FIFO input and Avalon MM from FIFO out to the DDR4.

Hi,
I didn't realize that you want to buffer counter data in DDR4 memory. But anyway case, it seems that data is send across clock domains without synchronization . Counter and FIFO are running in the PCIe (250 MHz) and DDR4 in the emif_usr_clk domain. I also don't recognize at first sight how DDR4 data path is multiplexed between clock crossing bridge and counter FIFO and how write control for counter is achieved.

Hi @Sijith,

Thanks for your update on the Signal Tap progress.

Yes, to connect FIFO to DDR4, it is through EMIF IP as the EMIF IP is used to interface with the memory devices.

Thanks.

Best Regards,

VenTing_Intel

Thank you VenTing,

It would be great if you could have a look to the Platform Designer connections for the modified design to check all connections makes sense for my design purpose (I mentioned earlier) by the time I will update you Signal Tap

Hi @Sijith,

I've looked into your modified design Qsys connection in Platform Designer.

Here are my findings and inquiries:

1. I'd like to ask where do you store the counter value/ source data. From which memory RAM that the Arria 10 Hard IP for PCIe can DMA read from?

As for a normal DMA write operation, the Write Data Mover requires the source address of the data is to be read. The write descriptors table requires the information of:

• Descriptor ID, ranging from 0-127

• Source address

• Destination address

• Size

You may refer to the user guide on the DMA Write operation: https://www.intel.com/content/www/us/en/docs/programmable/683425/18-0/datasheet.html

2. You can connect the FIFO to the EMIF IP to store the source data in the DDR4.

You may refer to the EMIF IP Example Design which I've included the steps to create the Example Design in the previous reply.

There is a clear Qsys connection provided in the Example Design between the data generator (which is Traffic Generator, tg in the Example Design) and EMIF IP for you as a reference when you're trying to connect the data generator to EMIF IP in your design.

3. After you confirm the FIFO to EMIF connection is correct, you may test the DMA read/write. Before that, please check the Signal Tap on the DDR to ensure that the source data generator is correctly stored in the DDR.

If the DMA operation is not working, please check out the PCIe reference design to compare your design with the reference design. In this reference design, there is a clear Qsys connection between the Arria 10 Hard IP for PCIe and the EMIF IP for you to refer to. And, the reference design has DMA transfers. The operation of this reference design shares the same operation as what you wanted to do in your modified design which is to perform DMA read/write from DDR.

Reference Design: https://www.intel.com/content/www/us/en/design-example/714949/intel-arria-10-fpga-pcie-3-0-x8-dma-design-example.html

Reference Design User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683554/18-0/an-829-mm-dma-reference-design.html

Lastly, if you're still failing to get the correct data value from DDR using DMA after following the connections in the above-mentioned Design Example and Reference Design, please send the Signal Tap result to clarify whether the issue is coming from the PCIe to DDR, or counter to DDR. Then, we can continue to debug from there.

I hope the above findings help you proceed with your project.

Thanks.

Best Regards,

VenTing_Intel

Hi @Sijith,

May I know if you have further questions on this case?

Thanks.

Best Regards,

VenTing_Intel

Hi VenTing,

Thank you very much. Actually I am facing some issue to get signal tap running. I would like to review you the procedure I followed. Please correct me if i went wrong in some steps or missing something.

1) Opened my counter+fifo+DMA trasfer example design (basically the modified design we were talking about so far) in Quartus Prime Pro.

2)Opened Platform designer and added Signal Tap IP and connected to the design. then validated system integrity and Generated HDL (clicking the GUI tab "Generate HDL") Then compiled the whole design in Quartus prime pro.

3)Opened the Quartus Prime Signal Tap Logical analyser and saved the .stp file. In the Signal Tap GUI, searched for nodes. But could not see any.

Am I missing some step? Do I want add some info in the .stp file manually?

Hi @Sijith,

In order to see the nodes, please ensure that you complete the correct pin assignment in the Pin Planner and compile the project beforehand.

Besides creating a Signal Tap Instance by HDL Instantiation, you can create the Signal Tap instance using the Signal Tap GUI.

Please refer to the steps in Section 2.3.1 to create a Signal Tap instance with the Signal Tap logic analyzer GUI.

User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/faq.html

Thanks.

Best Regards,

VenTing_Intel

Hi @Sijith,

Yes, you can run the Signal Tap by creating a Signal Tap instance with the Signal Tap logic analyzer GUI instead of using HDL instantiation (which is through the Signal Tap Logic Analyzer IP).

There are two ways to create a Signal Tap instance in this method:

1. Click Tools ➤ Signal Tap Logic Analyzer.

2. Click File ➤ New ➤ Signal Tap Logic Analyzer File.

You may follow the steps in Section 2.3.1 in the user guide.

Thanks.

Best Regards,

VenTing_Intel