A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi @Sijith,

Yes, I obtained the .qsys file from the attached ModifiedDesign.zip in the previous thread. May I know have you tried to run the Signal Tap to check the DDR? What is the observation?

The objective of generating the EMIF example design is to observe the connections on how the DDR store the incoming data because your qsys connection seemed off.

Since you have the next step which is using an external source to replace the counter for input data, I'd suggest you to directly go to this step. And then we can debug from there. Because it's not sure if we replace the counter with the external source, it might create other issues or not.

But if you want to use the counter to generate data and stream the data to DDR4 through FIFO, I think the counter should connect to the DDR4.

From the unmodified example design which you've run successfully, it already performed the DMA read and write operations to DDR4.

May I know what is protocol that you used to feed the data stream to FIFO and to DDR?

Thanks.

Best Regards,

VenTing_Intel