Sijith
Occasional ContributorJoined 3 years ago
User Profile
Occasional Contributor
User Widgets
Contributions
Re: Debugging PCIe DMA transfer example design
Hi VenTing, I have wrote to Terasic to enquire about the Driver and waiting for their reply. Sorry for bit delay as I was stuck with an emergency task. Now I restarted working on I am working on the DDR4 example design. I would like to have a couple more days to update. Thank you for the understanding. Regards Sijith E1.9KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi VenTing, Actually I am working on the DDR4 example design and anticipate a couple more days to finish. Would like to update you on this. About your previous reply, 1) Yes I was referring to 'Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4.cpp. Will just compiling this code will update the driver or I have to do something more. May I know which is the best place to ask question regarding the Driver modifications (Do you have experts providing support on the API drivers too?) for this example design? 2) In Chapter 7.3, the PCIe library module TERASIC_PCIE_AVMM.dll provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this DLL. I thought by disabling the writing part of API (PCIE_DmaWrite) in the `PCIE_DDR4.cpp.` file will do the work as it qualifies the description under `Chapter 7.3`. But not sure how to to modify the driver to initiate the DMA from the FPGA side. Any suggestion will be highly appreciated. Thank you very much Regards SE2.1KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi VenTing, The all change I made is in the "API.cc". file, instead of creating random number and sending that to DDR4, I retained only reading part of the code (I mean write DMA is disabled and only have read DMA), I am just curious that is this the thing I am suppose to do? If not what are the potential changes that we should make? Also, I would like to cross-check that during the Signal Tap capturing of the modified design, whether the Read DMA API is not suppose to run from host computer? (I mean to generate the trigger Avalon-MM read from the design (I mean from the unmodified part of the design) to the FiFO: I suspect the absence of this signal to FIFO cause no data from data generator (while running Signal Tap). Do you have any suggestion how to create those signals? Pls let me know if my question is not clear. I really would like to have little bit more time to provide updates on https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507. Thanks for the understanding Regards SE2.2KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi VenTing, I ran the DMA read test and could not verify that we could read data that is being written to FIFO. Just a question, as the Signal Tap does not show the data flow to FIFO when it connects to the DMA design (as I mentioned in the last message) should be expect the DMA read to work? I and currently I am trying to follow https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507 and will update you. Thank you Regards SE2.3KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi VenTing, First of all I think, the problem when hooking the Signal Tap up with data generator+ FIFO + DMA example design (modified DMA design) is I could see the data though the output data interface of the data generator + FIFO unit . 1) In this case (when data generator + FIFO) used as an isolated unit and add Signal Tap to it, I have been enforcing avalonmm_read_slave_address == 0 and avalonmm_read_slave_read == 1 using the button in the FPGA board. 2) But When we add this su-bunit (data generator + FIFO) with DMA example design (to form modified DMA transfer design), we could not see the data_generator_avalon_streaming_source_data[31..0] consistently displaying 00000000h. Here the avalonmm_read_slave_address and avalonmm_read_slave_read connected to the DMA design (not enforcing any values). As I am using same data-generator in case-1 and 2, I suspect its something to do with the state of avalonmm_read_slave_address and avalonmm_read_slave_read. I would like to know what we can do here? Let me know if you need any more information. Thank you Regards Sijith E5.8KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi VenTing, I am still working on it and could not resolve the issue you mentioned in the last message. I hope I can resolve it in a couple of days and will update you.. In the meantime, could you please have a look into the modified DMA transfer design (the .qsys file I sent you sometimes before) to see the signal connections I made are good. Regards Sijith6.4KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Thank you Ven ting. I was trying to create a signal tap instance with nodes at signals *avalon_streaming source data* (data from data generator to FIFO and related valid and ready signals), *fifo_read_outdata* (data out from the FIFO to the emif interface DDR4) and signals of ctrl_amm_0. But somehow the data wave form is not getting in the Signal Tap GUI Data tab. The clock I used to drive the signal tap is the clock to the datagenerator (CLKUSER_100). Anything I am missing? Also great if you could re-creat it to see anything missing? I am attaching the stp file and a screenshot and a video I believe the data from FIFO goes to the EMIF through signals of ctrl_amm_0. But I could not locate the data signal (some number of bit width ) in ctrl_amm_0. It would be great if you could point me that. Also, it would be great if you could look into the modified DMA transfer design file that once I sent to you (through google drive) and verify the connection I made in platform designer is reasonable (for sending the data from FIFO to the DDR4 memory element and then reading that data from host computer through DMA transfer through PCIe)7.1KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi Ven Ting, I would like to check if you could recreate the error I am seeing. Also I could see the compilation errors go away when I add nodes to the signals (from the screenshot you send... also see the screenshot `Capture_nodes_suggested.PNG) attached ) you suggested to my stp file. May I know why you suggested ctrl_amm_0 to add? Is it just for testing the compilation error I am seeing? Also, I am curious is it illegal to add nodes at address signals ? Also in signalTap GUI, some nodes (eg: signals of ctrl_amm_0 ) looks unassigned. (picture attached) is it something normal? Also do you have any suggestion on which nodes I can add to the stp file to visualize the data flow through my modified design (to test if the data generator created data goes to the DDR4 memory element correctly and then I can read that through PCIe DMA transfer from a host computer?). As a first step, I would like to visualize the data from data generator to DDR4, Any suggestion from your end to choose the signals to add nodes? Regards Sijith7.3KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi VenTing, Sorry for the confusion regarding the compilation error while adding Signal Tap. It is the modified DMA transfer example design that gives error while adding Signal Tap. I am attaching the stp1.stp file that on attaching with DMA example design gives the compilation error. Unfortunately right clicking the screenshot and clicking 'Open image in new tab' you attached goes to a Intel sign in page (see image Azure.png). It would be great if you could e-mail me the image. Regards Sijith7.5KViews0likes0CommentsRe: Debugging PCIe DMA transfer example design
Hi Ven Ting, I am sorry for a bit the delay in response currently I am traveling for a conference. currently, I have limited access to the system now. Will be able to address your questions well in two days. Just for a clarification, Can you please attach the original PCIe DMA transfer example design (without any modification) that you mentioned and include the steps to replicate the error for me to replicate the error at my end to further investigate the issue? Please let me know if you want to send the design via email May I know if you were asking for the design which I gives error when I add signal Tap and compile (Actually this is a design with DMA example design with FIFO and counter), --if this is the case I were using the design I shared you in google drive or you needed the PCIe DMA transfer example design (the original design without any modification). Thank you very much. Regards Sijith7.7KViews0likes0Comments