Debugging PCIe DMA transfer example design

Thank you Ven ting.

I was trying to create a signal tap instance with nodes at signals *avalon_streaming source data* (data from data generator to FIFO and related valid and ready signals), *fifo_read_outdata* (data out from the FIFO to the emif interface DDR4) and signals of ctrl_amm_0. But somehow the data wave form is not getting in the Signal Tap GUI Data tab. The clock I used to drive the signal tap is the clock to the datagenerator (CLKUSER_100). Anything I am missing? Also great if you could re-creat it to see anything missing? I am attaching the stp file and a screenshot and a video

I believe the data from FIFO goes to the EMIF through signals of ctrl_amm_0. But I could not locate the data signal (some number of bit width ) in ctrl_amm_0. It would be great if you could point me that.

Also, it would be great if you could look into the modified DMA transfer design file that once I sent to you (through google drive) and verify the connection I made in platform designer is reasonable (for sending the data from FIFO to the DDR4 memory element and then reading that data from host computer through DMA transfer through PCIe)