Forum Discussion

Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi, This is a extension of the discussion https://community.intel.com/t5/Programmable-Devices/Modifying-the-PCIe-DMA-transfer-example-design-for-Arria-10/m-p/1484799#M90698 and https://community.in...
Pcie
Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi VenTing,

Thank you very much. Actually I am facing some issue to get signal tap running. I would like to review you the procedure I followed. Please correct me if i went wrong in some steps or missing something.

1) Opened my counter+fifo+DMA trasfer example design (basically the modified design we were talking about so far) in Quartus Prime Pro.

2)Opened Platform designer and added Signal Tap IP and connected to the design. then validated system integrity and Generated HDL (clicking the GUI tab "Generate HDL") Then compiled the whole design in Quartus prime pro.

3)Opened the Quartus Prime Signal Tap Logical analyser and saved the .stp file. In the Signal Tap GUI, searched for nodes. But could not see any.

Am I missing some step? Do I want add some info in the .stp file manually?