A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi,

Thank you very much. Did not finished run SignalTap yet. Will update you very soon the result.

For feeding data from external source, I have to get the design and to develop data transfer design (QSFP+ to the FIFO then to DMA example design) strategy. So thought using counter to test the data transfer from FIFO to DMA transfer example design will be a quick validation I can do first.

In this reply message above (

community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1560274#M28411 )

He was mentioning about the absence of "valid data path from fifo to dma_wr_master ", this need only when we connect the FIFO to DMA, right? Or am I missing something?

The correct way to connect the FIFO to DDR4 is though the EMIF, right?

I have used the Avalon Streaming from counter to FIFO input and Avalon MM from FIFO out to the DDR4.