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fa_fpga_enthusiast
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1 month ago

Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5

Hello,

According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Center), the RMS jitter integrated from 10 kHz – 20 MHz, including spurs, is indicated as 522fs (maximum value).

We are using in our design a 156.25MHz clock (AX3DAF1-156.2500 from abracon), and the measured jitter is ~1ps currently.

 

We would like to know if this specification is for specific performances or if it’s a strict specification. (in our case, it’ll be for a 1G operation)

Thanks,
Best Regards

3 Replies

  • Hello,

     

    The 522fs RMS jitter (integrated from 10kHz to 20MHz, including spurs) for the GTS transceiver reference clock is a maximum value as defined in the Agilex 5 FPGAs and SoCs Device Data Sheet. This is generally treated as a strict specification to ensure reliable transceiver operation at all supported data rates. 

     

    Your measured clock jitter (~1ps RMS) is higher than the specified maximum (522fs). While your system may still operate at lower data rates (such as 1G), this operation is not explicitly guaranteed by Altera.
    The official specification is set to ensure optimal performance, low bit error rates (BER), and compliance across all supported use cases.

     

    Regards,

    Pavee

  • Hello,

     

    Hope you're doing well,

    Any updates from your end based on my previous response?

     

    Regards,

    Pavee

  • Hello,

     

    We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. 

    If you have a new question, feel free to open a new thread to get the support from Altera experts.
    Otherwise, the community users will continue to help you on this thread. 
    Thank you.

     

    Regards,

    Pavee