Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5

Hello,

According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Center), the RMS jitter integrated from 10 kHz – 20 MHz, including spurs, is indicated as 522fs (maximum value).

We are using in our design a 156.25MHz clock (AX3DAF1-156.2500 from abracon), and the measured jitter is ~1ps currently.

We would like to know if this specification is for specific performances or if it’s a strict specification. (in our case, it’ll be for a 1G operation)

Thanks,
Best Regards