About the System PLL in Agilex 5

Regarding the System PLL in Agilex 5, the reference clock input can be supplied not only from the dedicated transceiver input pins but also from HVIO pins.
However, when assigning the pins, the following Critical Warning occurs.

Critical Warning(24190):
User has specified a QSF location assignment to drive XPIN_GTS_CLK[0] using PIN_BK19.
The PIN_BK19 is on HVIO bank and is not optimal for HSSI PLL refclk usage.
Try to use the HSSI native local/global refclk IO instead. Additionally, this HVIO location assignment could cause the Reset Sequencer to be placed into a invalid shoreline.
To avoid this, besides the PLL refclk, you must also specify location assignment for the UX native refclk.

Is the operation acceptable, and what are the jitter characteristics?
Also, are there specific ways to address the Critical Warning?