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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5

Hello, According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Cent...
Transceiver
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
3 months ago

Hello,

 

The 522fs RMS jitter (integrated from 10kHz to 20MHz, including spurs) for the GTS transceiver reference clock is a maximum value as defined in the Agilex 5 FPGAs and SoCs Device Data Sheet. This is generally treated as a strict specification to ensure reliable transceiver operation at all supported data rates. 

 

Your measured clock jitter (~1ps RMS) is higher than the specified maximum (522fs). While your system may still operate at lower data rates (such as 1G), this operation is not explicitly guaranteed by Altera.
The official specification is set to ensure optimal performance, low bit error rates (BER), and compliance across all supported use cases.

 

Regards,

Pavee