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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5

Hello, According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Cent...
Transceiver
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 months ago

Hello,

 

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Altera experts.
Otherwise, the community users will continue to help you on this thread. 
Thank you.

 

Regards,

Pavee