A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi @Sijith,

I've looked into your modified design Qsys connection in Platform Designer.

Here are my findings and inquiries:

1. I'd like to ask where do you store the counter value/ source data. From which memory RAM that the Arria 10 Hard IP for PCIe can DMA read from?

As for a normal DMA write operation, the Write Data Mover requires the source address of the data is to be read. The write descriptors table requires the information of:

• Descriptor ID, ranging from 0-127

• Source address

• Destination address

• Size

You may refer to the user guide on the DMA Write operation: https://www.intel.com/content/www/us/en/docs/programmable/683425/18-0/datasheet.html

2. You can connect the FIFO to the EMIF IP to store the source data in the DDR4.

You may refer to the EMIF IP Example Design which I've included the steps to create the Example Design in the previous reply.

There is a clear Qsys connection provided in the Example Design between the data generator (which is Traffic Generator, tg in the Example Design) and EMIF IP for you as a reference when you're trying to connect the data generator to EMIF IP in your design.

3. After you confirm the FIFO to EMIF connection is correct, you may test the DMA read/write. Before that, please check the Signal Tap on the DDR to ensure that the source data generator is correctly stored in the DDR.

If the DMA operation is not working, please check out the PCIe reference design to compare your design with the reference design. In this reference design, there is a clear Qsys connection between the Arria 10 Hard IP for PCIe and the EMIF IP for you to refer to. And, the reference design has DMA transfers. The operation of this reference design shares the same operation as what you wanted to do in your modified design which is to perform DMA read/write from DDR.

Reference Design: https://www.intel.com/content/www/us/en/design-example/714949/intel-arria-10-fpga-pcie-3-0-x8-dma-design-example.html

Reference Design User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683554/18-0/an-829-mm-dma-reference-design.html

Lastly, if you're still failing to get the correct data value from DDR using DMA after following the connections in the above-mentioned Design Example and Reference Design, please send the Signal Tap result to clarify whether the issue is coming from the PCIe to DDR, or counter to DDR. Then, we can continue to debug from there.

I hope the above findings help you proceed with your project.

Thanks.

Best Regards,

VenTing_Intel