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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi, This is a extension of the discussion https://community.intel.com/t5/Programmable-Devices/Modifying-the-PCIe-DMA-transfer-example-design-for-Arria-10/m-p/1484799#M90698 and https://community.in...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @Sijith,


In order to see the nodes, please ensure that you complete the correct pin assignment in the Pin Planner and compile the project beforehand.


Besides creating a Signal Tap Instance by HDL Instantiation, you can create the Signal Tap instance using the Signal Tap GUI.

Please refer to the steps in Section 2.3.1 to create a Signal Tap instance with the Signal Tap logic analyzer GUI.

User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/faq.html


Thanks.

Best Regards,

VenTing_Intel


  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi VenTing,

    Correct pin assignment you meant is for the modified design, right? I have the pin assignment for the modified design (you can see that if you could open the ModifiedDesign file I shared you previously). And I assume I may not need to work on the pin assignment just after adding the Signal Tap IP into the design in the Platform Designer?

    I have a pin assignment (as I mentioned above I did not change any pin assignment after adding Signal Tap IP to the design) and did compile it too. But looks something is still missing.

    I went through the document and what I could understand is, we can add Signal Tap instances using GUI (So here we dont need to add signal tap IP to the Platform designer system) . Please correct me if I got wrong?

    Looking forward for your reply. Thank you.