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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi, This is a extension of the discussion https://community.intel.com/t5/Programmable-Devices/Modifying-the-PCIe-DMA-transfer-example-design-for-Arria-10/m-p/1484799#M90698 and https://community.in...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @Sijith,


Yes, you can run the Signal Tap by creating a Signal Tap instance with the Signal Tap logic analyzer GUI instead of using HDL instantiation (which is through the Signal Tap Logic Analyzer IP).

There are two ways to create a Signal Tap instance in this method:

1. Click Tools ➤ Signal Tap Logic Analyzer.

2. Click File ➤ New ➤ Signal Tap Logic Analyzer File.

You may follow the steps in Section 2.3.1 in the user guide.


Thanks.

Best Regards,

VenTing_Intel


  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thank you. I am able to see the nodes. The problem was my version of Quartus Prime Pro (18.1) has the Signal tap GUI with node finder NOT having LIST option instead it has search nodes option. So I hd to search for the needed nodes.

    There are still. some problems. After adding nodes to the instance and I could see thee message in Red in the Instance Manager of Signal Tap GUI "Start Rapid Recompile to Continue". But the problem is Rapid Recompile button is inactive as shown in attachment. Then I went for full compilation.

    After full compilation and programmed the board through JTAG. But I am getting the message in Instance manager "Program the device to continue". I did it multiple time and again I gets this message. I tried programming using Programmer from the Quartus Prime also (I have seen an intel community thread suggesting to do so https://community.intel.com/t5/Intel-Quartus-Prime-Software/Signal-tap-Program-the-device-to-continue/td-p/1276158 ), but it did not work for me as well. Screenshot attached. I have seen a community thread suggesting to do so.

    I have an additional question too. as I am trying to debug the counter fifo outputs at first, can I make an instance having signals that comes to fifo from the counter and from the counter-fifo to the DUT (PCIe DMA) as well? Or I need separate instances for them?

    Also, as my design having counter starting when SW[0] =1 (pull up), do I want to set SW[0]=1 after programming the device just before Running the Signal Tap?