A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi,
I didn't realize that you want to buffer counter data in DDR4 memory. But anyway case, it seems that data is send across clock domains without synchronization . Counter and FIFO are running in the PCIe (250 MHz) and DDR4 in the emif_usr_clk domain. I also don't recognize at first sight how DDR4 data path is multiplexed between clock crossing bridge and counter FIFO and how write control for counter is achieved.