Forum Discussion
Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello,
well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: Cannot synthesize dual-port RAM logic "ram" where 'ram' being : shared variable ram : memory_t; , well the problem is that when i use two clocks it gives this error, but when i use single clock, all goes well and i get no error. any thoughts over this problem? well the configuration of my system is, that i am using a Cyclone III - ep3c16q240 device, and first i want to test this RAM module alone, and further i will integrate it with my core, and then two different systems will be accessing this RAM with their specific clock. so this is the reason i need two clocks. will be looking forward for the support. thanks for your time. regards Ammar22 Replies
Altera_Forum--- Quote Start --- Do you have any other VHDL? The problem is more likely your code being incorrect, or you not doing the interface correctly What is the Cyclone 3 connected to? --- Quote End --- well, for now this is the code i am using, well may be there be an interfacing problem, but this is such a simple structure now, how could there be any interface problem. well the cyclone 3 is connected to a RAM and ARM7, over an address and data bus. also, all these components are on a custom designed pcb, i.e. fpga, ram, arm7, variable power supplies..etc..- Altera_Forum
Do you have any other VHDL?
The problem is more likely your code being incorrect, or you not doing the interface correctly What is the Cyclone 3 connected to? - Altera_Forum
Obviously, the "microcontroller stops working" issue can't be solved without tri-stating the data output to the bus. This would require in the first place a bidirectional (inout) port declaration, and secondly additional logic setting the output to (others => 'Z') when unselected. The tri-state operation isn't part of the RAM MegaFunction. On write, the cs would be decoded into WE signal, on read, it can be ignored by the RAM, only the bus tri-state matters.
- Altera_Forum
yes, this is the last changes i made to this vhdl, by adding a chip select (i just needed is because its being required in my design, any how, even i remove this,program get compiled, but i dont get proper results from fpga.
ok, if there somthing wrong with this code, then to omit this fear, i used the quatrus ii template for true dualport ram, and flash tht to fpga, reaction of fpga was same. so, where could be the problem now?? somthing missed by me or is it the FPGA??? also i tried some other small test codes on this fpga and they worked, and it was just to prove that fpga is alive or dead. - Altera_Forum
1. There is nothing specially about putting a design into an FPGA. It doesnt just "flash a ram", the entire chip is saved in flash. The problem here is probably down to your logic inside the FPGA.
2. I tried compiling you code, I got this error: info: ram logic "ram" is uninferred due to inappropriate ram size Plus you also have a chip select. There is no chip select in the HDL template provided by quartus. If you remove the chip select lines it compiles fine. memories inside the cyclone (and every other FPGA) do not have chip select. It will be up to you to modify your other logic to behave correctly. - Altera_Forum
hi, well, after being testing all the options, i am back with results,
1st i tried to check the option of MegaWizard, and i create a Dual port ram with two clocks, configured for Cyclone iii fpga, and yes i created it in a new project. then connected it to input and output pins, assign the pins to fpga-pinout and then i just flashed this dualport ram to my fpga, but it didnt work as it should, as soon as i connect this fpga to a micro-controller (ARM7) it stop working, and when i remove FPGA, then the micro-controller starts to work again, it seems as if their is a problem with the logic, or the way is it flashed? (is it possible? or is their a special way to flash a RAM module to fpga?) this is my first time to use FPGA as a memory module so this is why i have such questions. 2nd, is the question for the code i am using to make my custom dualport ram, well you can see as follows, when i use this code with a single clock then it is compiled, else it wont. and here it is being configured with one clock, so it is working fine. BUT the problem is the same when i flash this code to fpga, i get the same problem that micro-controller stops working. i also have checked the results on scope, and it appears that when i flash the fpga with any of the above configurations, it results like the pins of fpga change its state from low to high (during configuration) and then remain high. which doesn't seems normal to me, or is it okay??? - Altera_Forum
Doh
Yeah it does work fine Thicko here was trying to use separate read and write addresses. So yes, Quartus CAN infer true-dual port rams quite easily. Ammar - show us the code you were trying to use. - Altera_Forum
Oh I see, a surprizing result, the true dual port RAM template of the Quartus editor doesn't compile in Quartus. One would expect, it has been ever tested before.
P.S.: I started a new project with default settings from the scratch, and the template true_dual_port_ram_dual_clock compiled correctly. - Altera_Forum
Hmm, it appears you are correct. You cannot create a dual clocked, true dual port ram from code. You can have quartus infer a simple dual port ram (with write/read on clock1 and read only on the other clock2) but not write from both. it is also not listed in the coding templates.
Raise an enhancement request with altera. On a side note: to avoid all the stuff you get with the megawizard, instantiate rams directly in your code. You can control all the paramters yourself. Just include the library in your file: library altera_mf; use altera_mf.altera_mf_components.all; then browse to this directory in your quartus installation: /quartus/common/help/webhelp/master.htm#mergedProjects/hdl/mega/mega_list_mega_lpm.htm For Quartus releases pre v10.0, you could link to this help from the help menu via "megafunctions/lpm" but that menu choice has gone now, but the help files still exist. Anything listed as a "parameter" is just a generic. - Altera_Forum
Can you post your code - because what you are trying to do is possible. What is not possible is setting the read/write before write/read behaviour by using a shared variable (whereas you can with other other brand).
