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Honored Contributor
Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_ForumHonored Contributor
Honored Contributoryes, this is the last changes i made to this vhdl, by adding a chip select (i just needed is because its being required in my design, any how, even i remove this,program get compiled, but i dont get proper results from fpga.
ok, if there somthing wrong with this code, then to omit this fear, i used the quatrus ii template for true dualport ram, and flash tht to fpga, reaction of fpga was same. so, where could be the problem now?? somthing missed by me or is it the FPGA??? also i tried some other small test codes on this fpga and they worked, and it was just to prove that fpga is alive or dead.
