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Altera_Forum
Honored Contributor
Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_ForumHonored Contributor
Honored ContributorCan you post your code - because what you are trying to do is possible. What is not possible is setting the read/write before write/read behaviour by using a shared variable (whereas you can with other other brand).
