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Altera_Forum
Honored Contributor
Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_ForumHonored Contributor
Honored ContributorDo you have any other VHDL?
The problem is more likely your code being incorrect, or you not doing the interface correctly What is the Cyclone 3 connected to?
