True Dual Port Ram Synthesizes error with two clock signals

1. There is nothing specially about putting a design into an FPGA. It doesnt just "flash a ram", the entire chip is saved in flash. The problem here is probably down to your logic inside the FPGA.

2. I tried compiling you code, I got this error:

info: ram logic "ram" is uninferred due to inappropriate ram size

Plus you also have a chip select. There is no chip select in the HDL template provided by quartus. If you remove the chip select lines it compiles fine. memories inside the cyclone (and every other FPGA) do not have chip select.

It will be up to you to modify your other logic to behave correctly.