Forum Discussion

Honored Contributor

15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...

Altera_Forum

Honored Contributor

15 years ago

Oh I see, a surprizing result, the true dual port RAM template of the Quartus editor doesn't compile in Quartus. One would expect, it has been ever tested before.

P.S.: I started a new project with default settings from the scratch, and the template true_dual_port_ram_dual_clock compiled correctly.

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True Dual Port Ram Synthesizes error with two clock signals

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