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Honored Contributor
Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Do you have any other VHDL? The problem is more likely your code being incorrect, or you not doing the interface correctly What is the Cyclone 3 connected to? --- Quote End --- well, for now this is the code i am using, well may be there be an interfacing problem, but this is such a simple structure now, how could there be any interface problem. well the cyclone 3 is connected to a RAM and ARM7, over an address and data bus. also, all these components are on a custom designed pcb, i.e. fpga, ram, arm7, variable power supplies..etc..
