True Dual Port Ram Synthesizes error with two clock signals

--- Quote Start ---

Do you have any other VHDL?

The problem is more likely your code being incorrect, or you not doing the interface correctly

What is the Cyclone 3 connected to?

--- Quote End ---

well, for now this is the code i am using,

well may be there be an interfacing problem, but this is such a simple structure now, how could there be any interface problem.

well the cyclone 3 is connected to a RAM and ARM7, over an address and data bus.

also, all these components are on a custom designed pcb, i.e. fpga, ram, arm7, variable power supplies..etc..