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Honored Contributor
Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_ForumHonored Contributor
Honored ContributorObviously, the "microcontroller stops working" issue can't be solved without tri-stating the data output to the bus. This would require in the first place a bidirectional (inout) port declaration, and secondly additional logic setting the output to (others => 'Z') when unselected. The tri-state operation isn't part of the RAM MegaFunction. On write, the cs would be decoded into WE signal, on read, it can be ignored by the RAM, only the bus tri-state matters.
