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lambert_yu's avatar
lambert_yu
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1 year ago
Solved

There's minimum pulse violation for IOPLL under source synchronous operation mode

Hi,

I am facing one issue when I design the source synchronous lvds project.

case:

quartus II : 18.0.0 standard

speed : 1.6Gbps;

PLL : use external PLL

ref clk for PLL: 800Mhz

operation mode : source synchronous operation mode

After synthesis, there's minimum pulse violation for the refclk :

Slack : -0.3000; Actual width : 1.250ns; required width : 1.550ns; Type: Min Period; Clock : refclk ; Clock Edge : Rise; Target : *|twentynm_iopll_ip:twentynm_pll|fbclk_out~CLKENA0~EN;

From the required width, its clock frequency is 644Mhz (is close the Fout max value in the datasheet).

1) But from the data IOPLL User guide, only for zero_delay and external feedback mode, fbclk will be used. It means that fbclk* port will be exposed on the IP end?

2) So for Source synchronous mode, it only support 644*2Mbps?

3) If 2) is not right, how to resolve this issue?

Could someone please help me? Any response might give me some help, thanks!

BRs,

Lambert

Configuration
Generic Io

13 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    What is the target device?

    When you say "external PLL", what do you mean? Are you using a PLL in the device or getting a clock from somewhere else? Either way, why is an 800 MHz clock being used as a reference clock? That seems unusual and I don't know if an FPGA PLL can handle that.

    Your description of the setup is a bit unclear. Can you clarify exactly what you are doing and the setup?

    • lambert_yu's avatar
      lambert_yu
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      1 year ago

      Hi, sstrell

      I am sorry I made you confusion.

      target device : arria 10 : 10ax115n2f45e1sg

      For LVDS IP design, there's two PLL solution : external and internal; I used the external PLL solution. And just because it was usded in source synchronous design, and there's one following clock with data.The frequency of the following clock was 800Mhz (From arria 10 datasheet, the upper limit value is 800Mhz), and I made it as the reference clock for the IOPLL to generate fast clock, load clock and core clock which were used by lvds IP.

      For IOPLL, I used the source synchronous operation mode, and met the above issue (minimum pulse violation for the fbclk_out enable ).

      BRs,

      Lambert

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    May I know if the issue has been resolved and if you still need help with this case?


    Regards,

    Richard Tan


    • lambert_yu's avatar
      lambert_yu
      Icon for Contributor rankContributor
      1 year ago

      Hi, RichardTanSY

      I hadn't received any helpful information for this issue. Now current solution for this issue, I changed the PLL mode (from source sync -> direct mode). But for above issue, I expect that I could get the root cause.

      Best Regards,

      Lambert

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Could you share your design by archiving the project (Project > Archive Project) so that I can investigate it further.

    Also, we sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.
    Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.
    Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

    Regards,

    Richard Tan

    • lambert_yu's avatar
      lambert_yu
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      1 year ago

      Hi, Richard

      I coudn't export my design from internal network, and I only provide related configuration and related timing violation report, I don't know if it's okay for you to find the same issue. Related information as below figures:

      And if I change the Compensation mode from synchrous -> direct, there's no this minimum pulse issue.

      Best Regards,

      Lambert

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    May I know why you would like to use the Source synchronous mode?


    Fyi, PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.


    From the user guide link:

    https://www.intel.com/content/www/us/en/docs/programmable/683771/current/i-o-pll-specifications.html#mcn1413265701682__fn_LimitedInQIIByIOMaxFreq_IOPLL


    Although it states that the maximum frequency is 800 MHz for Input clock frequency:

    Do note that *This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.


    Additionally, could you check out this KDB article to see if it might be relevant to your case?https://www.intel.com/content/www/us/en/support/programmable/articles/000080391.html


    Without a provided design, I may need some time to replicate the issue.


    Regards,

    Richard Tan


    • lambert_yu's avatar
      lambert_yu
      Icon for Contributor rankContributor
      1 year ago

      Hi, Richard Tan

      I don't think so.

      Now I used the 10ax115n2f45e1sg, its speed grade should be -1. And the timing violation is about the pll's feedback path under source synchronous mode. And I think this feedback path use global route, and in the datasheet, its max frequency of feedback path is 644Mhz, so I think it's root cause for this minimum pulse violation.

      Best Regards,

      Lambert

    • lambert_yu's avatar
      lambert_yu
      Icon for Contributor rankContributor
      1 year ago

      Hi, Richard

      Thanks! That's great! I think I get what I want.

      Best Regards,

      Lambert

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed.


    Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.


    Thank you and have a great day!


    Best Regards,

    Richard Tan