Forum Discussion
ContributorCyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team,
I am not sure this is correct and did not found much info on Handbook.
Device 5CSXF6C6U23
CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated.
JTAG scan chain shows both HPS and FPGA devices.
JTAG program shows failed with wrong device address.
CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO.
JTAG scan chain shows both HPS and FPGA devices.
JTAG program shows successful result.
Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work?
I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable.
Please confirm this for best and safe device HW configuration.
Thanks,
Brian
9 Replies
AqidAyman_AlteraRegular Contributor
Hi Brian,
The Cyclone® V Pin Connection Guidelines state: “Connect these pins (VCCIO) to a power supply” Your test results align with the expectations, where when you left VCCIO floating, it can cause programming failure. For best and safest device hardware configuration, always connect VCCIO to the correct supply for every I/O bank, including BANK 5A/5B.
Reference: Cyclone® V GX, GT, E, SX, ST and SE Device Family Pin Connection Guidelines
Regards,
Aqid
BrianSune_FroumThen this is violating the HMC standard. When slot cards are not used the VCCIO could be floated and no supplied.
I cannot see the correlation between VCCIO and JTAG program fail.
VCCIO had nothing to do with JTAG scan unless JTAG is located in VCCIO 5A/5B.
VCCPGM or VCCIO BANK 3 is only the possible IO bank that can affected.
So which handbook or document have detail info on such.Thanks,
Brian
- AqidAyman_Altera
Hi Brian,
May I know what the error message you observed on the JTAG programs?
Regards,
Aqid
- AqidAyman_Altera
Hi Brian,
Since you left it as default, can you confirm that you tied those pins pull-up to VCCPGM and not VCCIO5A?Regards,
Aqid- BrianSune_Froum
You know this is making no sense?
I suggests Altera staff or actual FAE confirm.
You are simply guessing and not reading the document.Thanks,
Brian
- AqidAyman_Altera
Hi BrianSune_Froum ,
As per check in the device pinout file, there are some configuration pins located in BANK 5A, especially the INIT_DONE pin. If INIT_DONE is never asserted, it can cause configuration failure as per my understanding.
Regards,
Aqid- BrianSune_Froum
I am not sure you are Altera staff?
With basic electronic knowledge I guess open-drain should be easily understood.
With all do respect:"Output OD"
Disabled
Default:
Again Output OD:
Again off: Output OD
So with the project default turned off the possible input function pins that you would like to "guess"How could this introduce issue?
Brian
